base

v2021.10-rc5

驱动相关

1. Reset:Starfive-jh7110: Add reset driver for JH7110
   Support for reset controller on starfive JH7110 SoCs.
   commit: 56c86383dc88850ee2e5af197532939b861f573b

2. GPIO:Starfive-jh7110: Add GPIO driver for JH7110
   Support for GPIO controller on starfive JH7110 SoCs.
   Commit: 53d9e9530ae20f804b7ca2766ab125b42ad5bdb3

3. misc:OTP:Starfive-jh7110: Add driver for the Starfive otp controller
   Added a misc driver to handle OTP memory in Starfive SoCs.

没使用, 代码中用来读 eth0/1 MAC地址的, 但是没有启动

Commit: 4187fa6a2db9f82613758004fdab2b83b1161973

4. clk:starfive-jh7110: Add clock driver for JH7110
   Add a clock driver for StarFive JH7110 Soc platform.
   Commit: e9cef6c8ce31ff51099f23e2d628483cf762d728

5. reset:starfive: Adjust judgment conditions

The serial driver will call reset driver, udelay function will be called in reset driver,
but the timer is not init,so udelay function call will cases error.
Commit: c7889a100782db20e85f99f6471881cc51120dbc

6. clk:starfive-jh7110: remove unused clk

Remove unused clock in order to reduce code size.
Commit: 90afdef187afbf0af192288118d0abf542bc6301

7. clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macros

Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110.
Commit: 987a20bf9b0d146127559e0414c5d9607d41f601

8. clk:starfive-jh7110: Update pll0/pll1/pll2 clk

Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define
from clk-jh7110.c to jh7110_clk.dts
Commit: 76c3fe38884eabb095547ea5fd633855f221a2c5

9. reset:starfive-jh7110: Adjust the dependency of RESET_JH7110 macro

Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to
STARFIVE_JH7110.
Commit:

10. GPIO:Starfive-jh7110: Add macro definition

Add macro definition of GPIO
Commit: cafd9e471a9e6d7dae0fc5549a94e11e2aea221b

11. clk:starfive-jh7110: add JH7110_GMAC1_GTXC clk

Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110
Commit: 3b92ff69270562b86fba4e3e7f78f05ddc279ced

12. clk:starfive-jh7110: Update pll0/pll1/pll2 clk

Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c
Commit: 0b2572d9978f265b51a218f334434ab9fde41552

13. serial: ns16550: support a list of clk

Add a list of clk enable operation.
Commit: 98ef3602a1850c79d509fab405a673bf089e114e

14. clk:riscv:starfive: update uart3-uart5 clks

Update uart3-uart5 clks register info for StarFive JH7110 SoC.
Commit: 4806c43e7adae907b72eaedeb635fa2c03eef196

15. clk:jh7110: pll0 dynamically gets the frequency

pll0 dynamically gets the frequency.
Commit: d21940b4fcb226f80cec587794be4ca9e8c66a3f

16. reset:starfive:jh7110: Delete redundant logic

In the hardware design, the IPs RESET signal of jh7110 is divided into
two groups,one group is active high, and the other group is active low.
Commit: b8c8323ddde327c1ca67c20cc179990d63b88212

17. ram:starfive: Make ddr driver support 2G size

The ddr driver include two configs with 2G and 4G.Fist read the ddr size
config from the memory node in the dts,then match the right config and
do it.
Commit: b04743f040068be9b010bdb7acce67454c7bf8de

18. ram: starfive: jh7110: Replace the configuration operation for pll1 clk

Replace the configuration operation for pll1 clk with common api provide
by pll module.

Commit: 6c18803bcb898acd1f983315e9063209ba1d13e8

19. ram: starfive: Make DDR driver support 8G size

This patch include four items:
    1.rename the driver compatible name.
    2.reset action with the common API.
    3.clean up code to make it is closer to readable.
    4.add configuration to support 8G size
Commit: 10ee04a53553d97e698f36906844c243a1778b7f

18. clk:jh7110: update apb_bus clk relationship

The previous definition of apb_bus clock relationship is incorrect,so
update it.
Commit: 20f3a9aeb57d6237a1a19ae519e23f06d98f88ef

19. clk: starfive: jh7110: Modify the parameters of clk_register()

Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk.
Commit: 0c1fefaf48d0f58453dedda58dcd6ac206d7970f

20. driver:qspi: Switch the QSPI parent clock to pll0

Switch the QSPI parent clock to pll0 to improve the QSPI speed
Commit: bf2eae30d4aa6312e5a8578b12e8c3aa66a93fb0

21. ram: starfive: remove fdtdec_setup_mem_size_base call

Memory information has been obtained elsewhere, so remove
fdtdec_setup_mem_size_base call.
Commit: d204f230ac075b82e4d59271369245b5c5e58ecf

22. pinctrl: starfive: Add StarFive JH7110 driver

Add pinctrl driver for StarFive JH7110 SoC.
Commit: b69d2e5f56d1a2debb625bca32ac55df20a746ac

arch

1. riscv:soc:jh7110: Add support jh7110 soc.

Add StarFive JH7110 soc to support RISC-V arch
Commit: ef888a4df1dd200a95e8eb7aa90d0b08b89a1964

2. riscv:dts: add jh7110 support

Add dts support for jh7110. The starfive visionfive support is based on
jh7110 soc.
Commit: 632fd3126837ce40908de1b3c28d265e90367b71

3. riscv:starfive-jh7110: clear L2 LIM memory

Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
Commit: 00018eb98a12f2ebbbd25fcca0d1262939ebc769

4. arch: riscv: jh7110: add pll clk configuration for jh7110

Add common interface to set and get pll clk information for jh7110 soc.
Commit: 01bbc04d9d9c9e38e6dcc93b1e7dca57b5862c11

5. arch: riscv: jh7110: read ram size from eeprom

Update memory size information, which read from eeprom.

通过 read_eeprom 接口读到 ram size.
Commit: eb119d1553cfbc3fbccba4b46bdfcd25a4abd54e

6. riscv:starfive:jh7110: change gmac0 tx delay to 0xa

0xa will better match gmac0 tx in 1000M
Commit: 3d3363de0dd7b10d32f579031bbcc046adf4e7eb

board

1. board:starfive: add starfive visionfive board support

Add board support for StarFive VisionFive.
Commit: d3c8386d64f99863213087335b14be84c378957d

2. config:starfive-jh7110: add config file for jh7110

Add basic config option for StarFive VisionFive board.
Commit: e143a581a3cbdefd16771e9cc17cbd103c392a95

(x) 3. board:starfive: add rtc timer init (没使用 starfive_visionfive.c)

The rtc timer is used early in kernel, but the clk&reset driver is not
ready,so some clk&reset init is placed here.
Commit: f95a5cec9fd49737ce570098be96d0c4d5c40ea8

4. board:starfive: add starfive evb board support

Add board support for StarFive EVB.
Commit: e81a6b4b7a58f56772b48db74ccadfc77a733fe1

5. board:starfive: add clk init

Add clk init for ddr on JH7110 board
Commit: 0eddcac0de54ba6d7b73f4cef8fffc9ce86582e0

6. config:starfive-jh7110: update starfive evb board default config

Add DDR config to the default config for starfive evb board.
Commit: 845221c93ff817e702beeb571946b988092591b3

7. board:starfive: Modify dynamic alloc memory start addr in SPL

Modify the dynamic alloc memory start address from L2 LIM to DDR.
Commit: 41f9b1fe8d38ff8ab4f4e44aa953125834f9b41c

8. board:starfive: enable prefetcher and add two macaddress configuration

Add two macaddress for gmac0 and gmac1. Enable prefetcher for EVB board.
Commit: fb8cb55de36782b2db2f85741758e67061d14355

9. config:starfive-jh7110: add MICREL phy config to defconfig

Add MICREL phy config to defconfig for starfive EVB board.
Commit: 8a8168dd0c8404a6c3d72a924b7b4195c1cde8fb

10. board:starfive:evb: modify the GPIO configuration for sd module

Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc
to high frequency
Commit: 9ca1a627b4363ea3a08853cf1bbb821291ea0710

11. board:starfive:evb: update uart3-uart5 resets

Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive
JH7110 SoC.

Commit: 61f294b11cd12981b93a3a2deb8036f705332ae2

12. config:starfive-jh7110: add sd card boot config

Configure SD card boot parameters
Commit: 810b30254ca077d2f83ade0e30c51f60e9751945

13. configs: starfive_evb_defconfig: Support saveenv

Add saveenv config to Support saveenv

14. configs: starfive_visionfive2_defconfig: Support saveenv

Add saveenv config to Support saveenv
Commit: 6a74373a2368794cc52907ad9c77694cab6612be

14. configs: starfive: fix tftpboot file waite a long time for the first time

ARP_TIMEOUT is too large, then will waite a long time for the first time
Set ARP_TIMEOUT to 500 refer to others
Set PHY_ANEG_TIMEOUT needs longer aneg time for the 2nd phy
Commit: 5ae5eca975735a24fa04c00ec83f8cdbb408278e

15. board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmii

JH7110B needs switch gmac0/1 tx to rgmii phy.
Commit: bd7deb0588459f36cf774ed58a419a7efbc9d5e4

16. board:starfive:evb: add get_chip_type

Read the chip model from the rgpio3 and setenv “chip_vision”
Commit: 0dbe3fb0be546f2be7adaee6baf6d550fbba4e26

17. board:starfive:evb: Support using env to detect board version

JH7110B need tx_inverted by YT8521 phy, you need to read the chip
version to determine whether to use it.
Commit: ca91f535d48d02088ed4b5ad78eb343c0325b8c9

18. board: starfive: Support visionfive2
    Commit: ad9e1dc0ba91125117eb8d2a8474048c9632c530

19. board: starfive: visionfive: Add uart0 and jtag pinmux
    Commit: e67867c5f8062448479b6ae647aa6cfaab6134da

20. Support sd autoboot
    Commit: 59f872828b12d93b2636f2292bf0d7b2fa7088c5

21. board: starfive: Add i2c5 init for VisionFive2
    Commit: 642566351597bc9eca648de6ecdc6fed2a99e509

22. add ID_EEPROM supoort for VisionFive2
    Commit: 5f51c4024944bcd13211dd699cb89d3ea903e987

23. board: starfive: update gpio index base on visionfive2 A1.1

update sdio emmc uart0 gpio index base on visionfive2 new board A1.1
Commit: ef6e2f4194fc6d4cdb90cde3d9aad0feaf85847c

24. config: jh7110: read uboot by partition

uboot should be placed in partition-2
Commit: a4c05f0a0f3f67aeefe8c853f329dcd1981d39ec

25. Support scan to boot from sd card or emmc

Get bootmode, if bootmode is flash, then default boot from sd card.
Commit: 62abf7817bc66ed679534d75d904b029713cade3

26. Support boot from grub
    Commit: d4566c2f24b4df5702bb1ddf22f7d4b122f31280

27. board: starfive: Support auto to init gmac base on eeprom data
    Commit: 7e0268be6a6cd721230ea549e20588999170e37b

28. board: starfive: Add interface to get data from eeprom
    Commit: a25a1eb135b59a0a9050156831dc2bb6f735f063

29. board: starfive: visionfive2: add memory_addr and memory_size environment variable

In order to compatible visionfive2 board with different version,so the
memory size information read from eeprom. and save to environment
variable. The value which saved in environment variable will be used
to update the memory node in dts.
Commit: d4cfd564c23afae9efeb44a12d6a2be50b17d912

30. board:starfive:visionfive2: add jh7110_gmac_sel_tx_to_rgmii

JH7110B needs switch gmac0/1 tx to rgmii phy.
Commit: d4b261737e038bdf1bd234c776b9d864fdff5ebe

31. board:starfive:visionfive2: add get_chip_type

Read the chip model from the eerpom and setenv “chip_vision”
Commit: 48c7e4f1d064eb4f7b9493eda70897778a4e115f

32. board:starfive:visionfive2: Modify jh7110_gmac_init

JH7110B(chip_vision B) need switch gmac tx clk to rgmii phy.
Commit: b249d3bac3ab7524e2c066afdf1fef59d63dad5b

33. board:starfive:visionfive2: setenv uboot_fdt_addr

It is more convenient to dynamically modify uboot dts
Commit: 2a54b81bcaf7486aa8f75c04b67fcd809ca3dfa2

34. board:starfive:visionfive2: Support using env to detect board version

JH7110A do not need tx_inverted by YT8531 phy, you need to read the chip
version to determine whether to use it.
Commit: d0df544ccec590d8c18ebb9e63a36066af878dd5

35. board:starfive:visionfive2: Adaptive mem size in linux.

Visionfive2 has a 2/4/8G version. You need to read eeprom information in
uboot to obtain the size of mem, and modify the size of mem in linux
dts.
Commit: bcebb15d3a72480fd3871d9c3c597a4f249332d5

36. riscv:starfive:jh7110: change gmac0 tx delay to 0x9 for 1.2A.

0x9 will better match 1.2A gmac0 tx in 1000M
Commit: 6c8ec6a1fc2f14b756fb586c44ac4d8928a6ae82

37. qspi: improve qspi speed
    Commit: c42307e5639f9a6e7be41b2c504a7a635666397a

38. efi_loader: Enable RISCV_EFI_BOOT_PROTOCOL support

This adds support for new RISCV_EFI_BOOT_PROTOCOL to
communicate the boot hart ID to bootloader/kernel on RISC-V
UEFI platforms.
Commit: d2dc8ab69ef123955443fe63a58484f63e2c2d8b

39. configs:Enable CONFIG_CMD_NVEDIT_EFI and CONFIG_CMD_EFIDEBUG

Enable CONFIG_CMD_NVEDIT_EFI, CONFIG_CMD_EFIDEBUG, CONFIG_HEXDUMP and CONFIG_EFI_RISCV_BOOT_PROTOCOL.
Commit: dd3d4040c3a8e6ddf9a7d288145aaa6819fd1672

40. borad:jh7110:vf2: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddr

The jh7110 ddr starts from 0x40000000. Using 0x80000000 may cause the
CMA space to fail
Commit: bafe822cd4a4ffb82945e15a82a504010cb4c5af
Commit: c6a5bf91e2caf9f463a92a9198d8240a55caf8e8

41. board:starfive:Add gpio init
    board:starfive:Add gpio init

Fixing don’t detect wm8960 occasionally
Set scl/sda gpio output enable
Set drive strength to 12mA
Set gpio pull up
Commit: 226b62f65ea56d7946864140582885f0a5027a07

42. board:starfive:Modify GPIO_SD_SHIFT to GPIO_DS_SHIFT
    Modify GPIO_SD_SHIFT to GPIO_DS_SHIFT.
    Fix jh7110_gpio_init function.
    Commit: fb41a409823d96ef4b7db791764ece91ec407f7c

43. dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions

Add pinctrl definitions for StarFive JH7110 SoC.
Commit: 1288948b5409bd39fc90a6ff33b9e965518a7838

44. configs: Enable STARFIVE_PINCTRL

Enable STARFIVE_PINCTRL and PINCTRL_FULL
Commit: ee772d8aea46ebd0501a1acf3650da4bb68a897b

45. board:starfive:Remove usb/sdio0/sdio1 gpio init

Remove usb/sdio0/sdio1 gpio init.
Commit: 4cc82557a555cc4b99d0d5322122f7af3d798e59

46. configs: visionfive2 Enable STARFIVE_PINCTRL

visionfive2 Enable STARFIVE_PINCTRL and PINCTRL_FULL
Commit: 155942dbba0aa27065a12f76d71852bb6ba03943

47. dts:starfive:Visionfive2 Add pinctrl config

Add pinctrl config about sdio0/sdio1/uart0
Commit: 95589281b9c98534c26e339f8780b739c38b0d63

48. board:starfive:jh7110: default cpufreq is 1000Mhz.

The frequency of pll0 is set to 1000Mhz in the bootrom
Commit: 9b71c6f5fa0d96680a3329e24afab8b09ad685fb

49. board:starfive:jh7110: Set the CPU default frequency to 1000MHz

Set to 1000M to ensure the CPU can work normally under 0.8V`
voltage
Commit: 699c0a80340c59f6c68253966b0914cefd89baa2

50. board:starfive:visionfive2: configure vf2 for sysboot method

Dynamically edit dtb to load correct hardware information and uses sysboot method to boot to distro
Commit: dededaf458b8e38243ce8e8508d959621c56b985

net

1. net:phy: add 10/100M register configuration

Support 10/100M configuration.
Commit: dffb8ea8dd2860bb06e173e9f48f3f14b3b606f7

2. net: dwc_eth_qos:starfive: add jh7110 support

Add new configuration for jh7110 soc platform.
Commit: 461cd1afbed484002536e4f6cf985d47c33b09e8

3. net:phy:YUTAI: Add YT8511/yt8521 phy driver

This adds basic support for YUTAI YT8511/YT8521 phy.
Commit: 66ede3957c034d69fbbc24d22c19701c68b42cbf

4. net:phy:YUTAI: Add YT8511/yt8521 phy init

Add phy init for YUTAI YT8511/YT8521.
Commit: 17a76df9975a5cf1dfad3cd02c9fd7aa49471001

5. net:phy:YUTAI: Add delay chain

Add tx/rx delay chain for YUTAI 8521
Commit: f785501c47181e5918e8464edfedfee3a1c43566

6. net: dwc_eth_qos:starfive: update clk init

Modify the clk init code for StarFive JH7110 platform.
Commit: db61964dc2ecbbc9fb7fb89f0eed597b4429c82f

7. net:dwc_eth_qos:starfive: remove phy-reset-gpio set

Phy-reset-gpio set is unused in JH7110
Commit: 87549bf09316b49ec19e7e9c289d6138deb3de1c

8. riscv:dts:starfive-jh7110: add ethernet-phy delay_chain config

Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB
board.

Commit: 6bf1de16aa64caef1f8fab2876fa83a6f12f0917

9. net:phy:YUTAI: change tx delay config

Modify the tx delay configuration.
Commit: b239f16521b95137a46d6bfb59d8214da3f0620b

10. net:phy:motorcomm: Support modifying RGMII_TX_CLK delay train from dts

support use original or inverted RGMII_TX_CLK delay train.
10M/100M/1000M can be configured independently.
Commit: fe0ba7e18ed6fddfa4fe22e93cb1827d7a73a7a7

11. net: phy: Support YT8531 Gigabit Ethernet
    Commit: b8632bd416725e28894ef5bb8b4ede92d4f5bfd4

12. net:stmmac:dwc-qos: add support for external rmii_rtx clocks

JH7110A use external rmii_rtx clk for tx clk on 100M/10M mode.
Commit: 1cbbd9f9decb9815b29a77e42db7a0792c239883

usb

1. usb:cdns3:Add StarFive wrapper driver for CDNS USB3 controller

Add driver to handle StarFive specific wrapper for Cadence USB3 controller
present on JH7110 SoC.
Commit: 11477926e35cb478977edd67181f6b16ce5a1afc

2. board:starfive:evb: add usb init config

Add usb init config for starfive EVB board. Default set to USB2.0
Commit: 5531f12c6efc79817914bf96f5b755840402e8c7

dts

1. riscv:dts: update clk&reset properties

Synchronize the kernel dts file
Commit: a014f51a8627f564caaa57654a56919972851c90

2. riscv:dts: update clk&reset properties

Synchronize the kernel dts file
Commit: becd46e20807c56a071be1eaab897bcaeb178c31

3. riscv:dts:starfive-jh7110: add ddr device node

Add ddr device node for JH7110.
Commit: 6f0b30d82cebe9457d42f442846b716fcca65beb

4. riscv:dts:starfive-jh7110: Modify sd node configuration

Modify SD&EMMC node configuration on Starfive EVB board.
Commit: 967e3296edfa01d8109213f5dd89b7bc9e6c1801

5. riscv:dts:starfive-jh7110: modify Model and riscv,isa info

Change Model to “StarFive JH7110 EVB”, and change riscv,isa to
“rv64imafdcbsux”
Commit: 283a338dce45e9db43e9c7a40eaf56482f5d8d3a

6. riscv: dts: jh7110: Add reset property to DDR control node

Add reset property configuration to DDR control device tree node.
Commit: 7efb109f1dd2f9a34da35392338ba3290764ec5c

7. dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.

JH7110B requires tx_inverted_10/100/1000 configuration, and different
parameters
may be required in 10M/100M/1000M mode.

This parameter supports JH7110B+YT8531PHY by default. Other boards can
modify the parameters of the tx_inverted_10/100/1000 to obtain support.

If you do not configure tx_inverted_10/100/1000 in dts, the default is 0.
Commit: 460fe5dd0b3a288eb58bee6874683288bef671ce

8. riscv:dts:starfive-visionfive2: Add ethernet-phy node to set delay_chain
   configuration

Add ethernet-phy subnode to gmac node, so the delay_chain configuration
is passed through the ethernet-phy node.
Commit: c0f7ad1b409cbae54b2d0272d57e4ee55e9917ec

9. dts:starfive:jh7110: set gmac phy tx_inverted for JH7110B+YT8531PHY.

JH7110B requires tx_inverted_10/100/1000 configuration, and different parameters
may be required in 10M/100M/1000M mode.

Commit: a953d55d4b0ad37af2b1f2e673813e08ec999df6

10. dts: pmic: add axp15060 pmic config in vf2 uboot dts

add axp15060 pmic dts config for opensbi power managment
used.
Commit: b50de2c0ae0c5e6e1e52853960d232005ddb17db

11. dts:starfive:Add pinctrl config

Add pinctrl config about usb/sdio0
Commit: 68dc79062721456f05815278dd428c2355ebd132

arch/riscv/dts/jh7110-u-boot.dtsi
arch/riscv/dts/jh7110.dtsi
arch/riscv/dts/jh7110_clk.dtsi
arch/riscv/dts/starfive_visionfive-u-boot.dtsi
arch/riscv/dts/starfive_visionfive.dts

spl

1. ram:starfive: add ddr driver

Add driver for JH7110 to support ddr initialization in SPL.
Commit: b8ceeb8238c4db755c2a3e5fe178568bd2d4c568

1. SPL:riscv:starfive-jh7110: Adjust CPU working frequency

Adjust CPU working frequency from 1G to 1.25G for starfive EVB board.
Commit: c43d28132317bd745a485543569e80d4bcfee018

2. spl:gpio: Set GPIO domain0-3 voltage to 1.8V

The default GPIO domian0-3 voltage is 3.3V, which is controlled by 4
bits. 0 means 3.3.V, 1 means 1.8V.
Commit: fc05902d00e58c4c85a34d8ab44dc42eef51cdc6

3. spl: satrfive: bus_root switch to pll2.

High-speed emmc/sdio support
Commit: 1f6321dbaf5951fd0ffce1bf320000c8be9280f6

4. SPL:starfive-jh7110: Modify the default division factor of sdcard clk

Modify the default division factor of sdcard clk to 4.
Commit: 16178e355d396994e63546d552a5c75e4aad71c0

5. SPL:reset:starfive-jh7110: support reset in SPL

Update Kconfig to support reset in SPL for StarFive JH7110 SoC.
Commit: abd35ca6d33fb5df1f413b5466b315a92fa36f4f

6. spl:starfive: remove function spl_cpu_fre_150/125

replace them with spl_cpu_set_rate.
Commit: 90a8248c00836a25ddc3e3bca3a83f41f61a4cd3

7. spl:starfive: Add support for different CPU frequencies.

The cpu uses 1.25G by default.
Commit: 66107c3e05e8804971bd14c575a509dbd816ae37

8. spl:jh7110: Modify cpu frequency should be before switching pll
   Commit: 0fb1b1ba8184d410749a657c932a4bb7f107a8d2

9. spl: starfive: jh7110: switch pll2 to 1188M

Switch the pll2 clk to 1188M with the comm pll interface on JH7110.
Commit: 47e689908a5cca249c036138cc0f4bde014576a2

11. spl:starfive:jh7110: Improved GMAC0/1 TX I/O PAD capability

JH7110B requires a higher IOPAD capability in 1000M mode.
Commit: 945a1c00275fa1e81678dfa54d430f0877cd8146

12. i2c: designware: support SYS_I2C_DW in SPL

Add SYS_I2C_DW driver to support in SPL.
Commit: a98d92b150695ab214bb119a9afc07d38d136a1f

13. SPL: starfive: jh7110: add i2c init in SPL

Add basic init before used by other modules in SPL.
Commit: 0cb0bb697c65553464dc1b20f656da56281942db

14. riscv: dts: starfive: add i2c5 node in SPL

Add i2c5 device configuration　to device tree which used by SPL.
Commit: 352b4397d389e41f1d170c43a9b9139a8fbb79f2

15. configs: starfive: visionfive2: enable i2c eeprom in SPL

Enable I2C and EEPROM driver in SPL.

drivers/misc/i2c_eeprom.c

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eeprom@50 {
        compatible = "atmel,24c04";
        reg = <0x50>;
        pagesize = <0x10>;
};

Commit: e7083b7199dba53255c4b59ee55f767e071133af

16. spl:starfive:jh7110: Improved GMAC0 TX I/O PAD capability

JH7110B requires a higher IOPAD capability in 1000M mode.
Commit: b949c9b66c4d453ed0d454c7b5ee5c0aea280c28
Commit: 9b8509bfef25819f9be0015013370aec69f6ba5b

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/ {
        compatible = "starfive,jh7110";
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        model = "StarFive VisionFive V2";

        osc {
                compatible = "fixed-clock";
                #clock-cells = <0x0>;
                clock-frequency = <0x16e3600>;
                phandle = <0x8>;
        };

        gmac1_rmii_refin {
                compatible = "fixed-clock";
                #clock-cells = <0x0>;
                clock-frequency = <0x2faf080>;
                phandle = <0x9>;
        };

        stg_apb {
                compatible = "fixed-clock";
                #clock-cells = <0x0>;
                clock-frequency = <0x30d4000>;
                phandle = <0xa>;
        };

        gmac0_rmii_refin {
                compatible = "fixed-clock";
                #clock-cells = <0x0>;
                clock-frequency = <0x2faf080>;
                phandle = <0xb>;
        };

        cpus {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                timebase-frequency = <0x3d0900>;
                phandle = <0x2c>;

                cpu@0 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <0x0>;
                        d-cache-block-size = <0x40>;
                        d-cache-sets = <0x40>;
                        d-cache-size = <0x2000>;
                        d-tlb-sets = <0x1>;
                        d-tlb-size = <0x28>;
                        device_type = "cpu";
                        i-cache-block-size = <0x40>;
                        i-cache-sets = <0x40>;
                        i-cache-size = <0x4000>;
                        i-tlb-sets = <0x1>;
                        i-tlb-size = <0x28>;
                        mmu-type = "riscv,sv39";
                        next-level-cache = <0x1>;
                        riscv,isa = "rv64imacu";
                        tlb-split;
                        status = "okay";
                        phandle = <0x2d>;

                        interrupt-controller {
                                #interrupt-cells = <0x1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                                phandle = <0x3>;
                        };
                };

                cpu@1 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <0x1>;
                        d-cache-block-size = <0x40>;
                        d-cache-sets = <0x40>;
                        d-cache-size = <0x8000>;
                        d-tlb-sets = <0x1>;
                        d-tlb-size = <0x28>;
                        device_type = "cpu";
                        i-cache-block-size = <0x40>;
                        i-cache-sets = <0x40>;
                        i-cache-size = <0x8000>;
                        i-tlb-sets = <0x1>;
                        i-tlb-size = <0x28>;
                        mmu-type = "riscv,sv39";
                        next-level-cache = <0x1>;
                        riscv,isa = "rv64imafdcbsux";
                        tlb-split;
                        status = "okay";
                        phandle = <0x2e>;

                        interrupt-controller {
                                #interrupt-cells = <0x1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                                phandle = <0x4>;
                        };
                };

                cpu@2 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <0x2>;
                        d-cache-block-size = <0x40>;
                        d-cache-sets = <0x40>;
                        d-cache-size = <0x8000>;
                        d-tlb-sets = <0x1>;
                        d-tlb-size = <0x28>;
                        device_type = "cpu";
                        i-cache-block-size = <0x40>;
                        i-cache-sets = <0x40>;
                        i-cache-size = <0x8000>;
                        i-tlb-sets = <0x1>;
                        i-tlb-size = <0x28>;
                        mmu-type = "riscv,sv39";
                        next-level-cache = <0x1>;
                        riscv,isa = "rv64imafdcbsux";
                        tlb-split;
                        status = "okay";
                        phandle = <0x2f>;

                        interrupt-controller {
                                #interrupt-cells = <0x1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                                phandle = <0x5>;
                        };
                };

                cpu@3 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <0x3>;
                        d-cache-block-size = <0x40>;
                        d-cache-sets = <0x40>;
                        d-cache-size = <0x8000>;
                        d-tlb-sets = <0x1>;
                        d-tlb-size = <0x28>;
                        device_type = "cpu";
                        i-cache-block-size = <0x40>;
                        i-cache-sets = <0x40>;
                        i-cache-size = <0x8000>;
                        i-tlb-sets = <0x1>;
                        i-tlb-size = <0x28>;
                        mmu-type = "riscv,sv39";
                        next-level-cache = <0x1>;
                        riscv,isa = "rv64imafdcbsux";
                        tlb-split;
                        status = "okay";
                        phandle = <0x30>;

                        interrupt-controller {
                                #interrupt-cells = <0x1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                                phandle = <0x6>;
                        };
                };

                cpu@4 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <0x4>;
                        d-cache-block-size = <0x40>;
                        d-cache-sets = <0x40>;
                        d-cache-size = <0x8000>;
                        d-tlb-sets = <0x1>;
                        d-tlb-size = <0x28>;
                        device_type = "cpu";
                        i-cache-block-size = <0x40>;
                        i-cache-sets = <0x40>;
                        i-cache-size = <0x8000>;
                        i-tlb-sets = <0x1>;
                        i-tlb-size = <0x28>;
                        mmu-type = "riscv,sv39";
                        next-level-cache = <0x1>;
                        riscv,isa = "rv64imafdcbsux";
                        tlb-split;
                        status = "okay";
                        phandle = <0x31>;

                        interrupt-controller {
                                #interrupt-cells = <0x1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                                phandle = <0x7>;
                        };
                };
        };

        soc {
                compatible = "simple-bus";
                #address-cells = <0x2>;
                #size-cells = <0x2>;
                #clock-cells = <0x1>;
                ranges;
                phandle = <0x32>;

                clint@2000000 {
                        compatible = "riscv,clint0";
                        reg = <0x0 0x2000000 0x0 0x10000>;
                        reg-names = "control";
                        interrupts-extended = <0x3 0x3 0x3 0x7 0x4 0x3 0x4 0x7 0x5 0x3 0x5 0x7 0x6 0x3 0x6 0x7 0x7 0x3 0x7 0x7>;
                        #interrupt-cells = <0x1>;
                        phandle = <0x34>;
                };

                clock-controller {
                        compatible = "starfive,jh7110-clkgen";
                        reg = <0x0 0x13020000 0x0 0x10000 0x0 0x10230000 0x0 0x10000 0x0 0x17000000 0x0 0x10000>;
                        reg-names = "sys", "stg", "aon";
                        clocks = <0x8 0x9 0xa 0xb>;
                        clock-names = "osc", "gmac1_rmii_refin", "stg_apb", "gmac0_rmii_refin";
                        #clock-cells = <0x1>;
                        status = "okay";
                        phandle = <0xf>;
                };

                spi@13010000 {
                        compatible = "cdns,qspi-nor";
                        #address-cells = <0x1>;
                        #size-cells = <0x0>;
                        reg = <0x0 0x13010000 0x0 0x10000 0x0 0x21000000 0x0 0x400000>;
                        clocks = <0xf 0x5a>;
                        clock-names = "clk_ref";
                        resets = <0x10 0x3e 0x10 0x3d 0x10 0x3f>;
                        resets-names = "rst_apb", "rst_ahb", "rst_ref";
                        cdns,fifo-depth = <0x100>;
                        cdns,fifo-width = <0x4>;
                        spi-max-frequency = <0xee6b280>;
                        status = "okay";
                        phandle = <0x35>;

                        nor-flash@0 {
                                compatible = "jedec,spi-nor";
                                reg = <0x0>;
                                spi-max-frequency = <0x5f5e100>;
                                cdns,tshsl-ns = <0x1>;
                                cdns,tsd2d-ns = <0x1>;
                                cdns,tchsh-ns = <0x1>;
                                cdns,tslch-ns = <0x1>;
                                phandle = <0x36>;
                        };
                };

                serial@10000000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x0 0x10000000 0x0 0x10000>;
                        reg-io-width = <0x4>;
                        reg-shift = <0x2>;
                        clocks = <0xf 0x92 0xf 0x91>;
                        clock-names = "baudclk", "apb_pclk";
                        resets = <0x10 0x53 0x10 0x54>;
                        status = "okay";
                        reg-offset = <0x0>;
                        current-speed = <0x1c200>;
                        clock-frequency = <0x16e3600>;
                        phandle = <0x3e>;
                };

                i2c@12050000 {
                        compatible = "snps,designware-i2c";
                        reg = <0x0 0x12050000 0x0 0x10000>;
                        clocks = <0xf 0x12a 0xf 0x8f>;
                        clock-names = "ref", "pclk";
                        resets = <0x10 0x51>;
                        #address-cells = <0x1>;
                        #size-cells = <0x0>;
                        status = "okay";
                        clock-frequency = <0x186a0>;
                        i2c-sda-hold-time-ns = <0x12c>;
                        i2c-sda-falling-time-ns = <0xbb8>;
                        i2c-scl-falling-time-ns = <0xbb8>;
                        auto_calc_scl_lhcnt;
                        phandle = <0x4b>;

                        eeprom@50 {
                                compatible = "atmel,24c04";
                                reg = <0x50>;
                                pagesize = <0x10>;
                        };
                };

                sdio0@16010000 {
                        compatible = "snps,dw-mshc";
                        reg = <0x0 0x16010000 0x0 0x10000>;
                        clocks = <0xf 0x5b 0xf 0x5d>;
                        clock-names = "biu", "ciu";
                        resets = <0x10 0x40>;
                        reset-names = "reset";
                        fifo-depth = <0x20>;
                        bus-width = <0x8>;
                        status = "okay";
                        phandle = <0x4d>;
                };

                sdio1@16020000 {
                        compatible = "snps,dw-mshc";
                        reg = <0x0 0x16020000 0x0 0x10000>;
                        clocks = <0xf 0x5c 0xf 0x5e>;
                        clock-names = "biu", "ciu";
                        resets = <0x10 0x41>;
                        reset-names = "reset";
                        fifo-depth = <0x20>;
                        bus-width = <0x4>;
                        status = "okay";
                        phandle = <0x4e>;
                };

                reset-controller {
                        compatible = "starfive,jh7110-reset";
                        reg = <0x0 0x13020000 0x0 0x10000 0x0 0x10230000 0x0 0x10000 0x0 0x17000000 0x0 0x10000 0x0 0x19810000 0x0 0x10000 0x0 0x295c0000 0x0 0x10000>;
                        reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
                        #reset-cells = <0x1>;
                        status = "okay";
                        phandle = <0x10>;
                };

                dmc@100b0000 {
                        compatible = "starfive,jh7110-dmc";
                        reg = <0x0 0x15700000 0x0 0x10000 0x0 0x13000000 0x0 0x10000>;
                        resets = <0x10 0x26 0x10 0x27 0x10 0x28>;
                        reset-names = "axi", "osc", "apb";
                        clock-frequency = <0x855>;
                        phandle = <0x71>;
                };
        };

        aliases {
                spi0 = "/soc/spi@13010000";
                mmc0 = "/soc/sdio0@16010000";
                mmc1 = "/soc/sdio1@16020000";
                i2c0 = "/soc/i2c@12050000";
        };

        chosen {
                stdout-path = "/soc/serial@10000000:115200";
        };

        memory@80000000 {
                device_type = "memory";
                reg = <0x0 0x40000000 0x1 0x0>;
        };

        firmware {
                spi0 = "/soc/qspi@11860000";
        };

        config {
                u-boot,spl-payload-offset = <0x100000>;
        };
};

u-boot 中evb 相关的组件

1. pinctrl 相关
   drivers/pinctrl/starfive/*
   pinmux 等 gpio_set_value
   Figure 3-1 Pin Map 040

2. dram 相关
   arch/riscv/cpu/jh7110/dram.c
   只是获取大小, 基址等
   没有进行ddr 初始化, 不涉及 drivers/ram/starfive/ 下的代码

3. clk 相关 pll
   drivers/clk/starfive/clk-jh7110.c
   dts “starfive,jh7110-clkgen”
   reg : aon sys stg

4. gpio
   drivers/gpio/starfive-gpio.c
   GPIO Function Description 055
   Full Multiplexing 060

5. eeprom
   board/starfive/visionfive2/visionfive2-i2c-eeprom.c
   设置board相关信息, 如 mac0_address mac1_address pcb_revision product_id 等

6. arch 相关
   arch/riscv/cpu/jh7110/
   主要是pll

7. 复位相关
   drivers/reset/reset-jh7110.c

Table 5-4 Reset Source 071

8. net usb 相关
   drivers/usb/cdns3/cdns3-starfive.c (新增 cdns usb3 controller 驱动)
   drivers/net/phy/motorcomm.c (新增 net:phy:YUTAI 驱动 Add YT8511/yt8521 phy driver)
   drivers/net/dwc_eth_qos.c :

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static struct eqos_ops eqos_jh7110_ops = {
	.eqos_inval_desc = eqos_inval_desc_generic,
	.eqos_flush_desc = eqos_flush_desc_generic,
	.eqos_inval_buffer = eqos_inval_buffer_generic,
	.eqos_flush_buffer = eqos_flush_buffer_generic,
	.eqos_probe_resources = eqos_probe_resources_jh7110,
	.eqos_remove_resources = eqos_remove_resources_jh7110,
	.eqos_stop_resets = eqos_stop_resets_jh7110,
	.eqos_start_resets = eqos_start_resets_jh7110,
	.eqos_stop_clks = eqos_stop_clks_jh7110,
	.eqos_start_clks = eqos_start_clks_jh7110,
	.eqos_calibrate_pads = eqos_null_ops,
	.eqos_disable_calibration = eqos_null_ops,
	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
};

struct eqos_config __maybe_unused eqos_jh7110_config = {
	.reg_access_always_ok = false,
	.mdio_wait = 10,
	.swr_wait = 50,
	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
	.axi_bus_width = EQOS_AXI_WIDTH_64,
	.interface = eqos_get_interface_jh7110,
	.ops = &eqos_jh7110_ops
};

9. board 相关
   board/starfive/evb/starfive_visionfive2.c
   board_init_r
   enable_caches();
   enable_prefetcher();
   jh7110_jtag_init();
   jh7110_timer_init();
   jh7110_usb_init(true);
   jh7110_i2c_init(5);
   jh7110_gpio_init();
   misc_init_r
   set_uboot_fdt_addr_env
   board_late_init
   get_boot_mode();
   jh7110_gmac_init(get_chip_type(), get_board_type());
   env_set_hex(“memory_addr”, gd->ram_base);
   env_set_hex(“memory_size”, gd->ram_size);

10. 启动相关
    include/configs/starfive-visionfive2.h
    VF2_DISTRO_BOOTENV env相关配置如 kernel_addr_r 等
    “bootcmd=” CONFIG_BOOTCOMMAND

11. cache相关
    drivers/cache/cache-sifive-ccache.c
    arch/riscv/lib/cache.c
    arch/riscv/lib/sifive_cache.c

spl中evb 相关组件

1. pll 相关修改
   arch/riscv/cpu/jh7110/pll.c
   arch/riscv/cpu/jh7110/spl.c

PLL0 PLL1 PLL2
Figure 5-2 Clock Structure 073

2. dram相关初始化
   arch/riscv/cpu/jh7110/dram.c
   drivers/ram/starfive/*
   ddr_phy ddrcsr_boot ddr_csr_cfg/ddr_csr_cfg1/ddr_csr_cfg2/ddr_csr_cfg3 dddrc_clock (controller 配置)

board/starfive/evb/spl.c

spl 中没有使用pinctrl

3. 复位相关
   drivers/reset/reset-jh7110.c
   如ddr 初始化时会用到 rst_osc rst_apb rst_axi

4. cpu相关
   arch/riscv/lib/sifive_clint.c
   arch/riscv/lib/cache.c
   arch/riscv/lib/interrupts.c
   arch/riscv/lib/smp.c
   ? drivers/timer/riscv_timer.c
   drivers/timer/sifive_clint_timer.c

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Configuration

L2 Cache 集成在 CM 中，与外部 memory 通过256-bit AXI 接口连接

L1 cache 配置

l1 cache 配置

注意:

l1-dcache 和 l1-icache 均不支持 “Fetch and Lock”, mcache 对 icache 和 l1-dcache 执行 Fecth and lock 操作相当于执行 nop.
由于不支持 lock, 所以不用对 tag 进行初始化? 只需要执行 MGINVI 或 FENCE.I 将 icache dcache invalidate 即可.

在 mipsconfig1 csr 中包含了 l1 cache 的配置

• L2C  见下面的 GCR_L2_CONFIG 寄存器
• IS 只读, I-cache set 数, set = 2^(IS+6) if IS 不为 7, 如果IS=7, set=32
• IL 只读, I-cache line size, line_size = 2^(IL+1)
• IA 只读, I-cache way , way = IA + 1
• DS 只读, D-cache set 数,  set = 2^(DS+6) if DS 不为 7, 如果IS=7, set=32
• DL 只读, D-cache line size, line_size = 2^(DL+1)
• DA 只读, D-cache way, way = DA + 1

l2 cache 配置

SET_SIZE LINE_SIZE ASSOC 都是只读的,  软件不能进行配置, L2_BYPASS 可写配置来禁用 L2 cache.
软件可以读 SET_SIZE LINE_SIZE ASSOC 来获取 l2 的配置.

Feature

支持 lock.
支持 bypass 模式, 可以禁用 L2 cache.
通过配置 GCR_L2_CONFIG (GCR offset 0x0130) 寄存器来配置 l2 cache

l1 cache CCA - pma

pma0cfg - pma63cfg

控制 pmp 配置地址的 CCA 属性

应该是配置的 L1 cache 的 CCA. 对应 hart 的 CCA 属性
如果对应的 pmp entry 没有配置, 则默认返回 UC (uncached)

• Bit [3] S 位代表支持预测
• Bit [2:0] CCA 属性
  • 0 为 cache_enable
  • 2 为 cache disable
  • 3 为 uncache 加速, 启用 store buffer?
    • uncached Accelerated (code #7 ): Uncached stores are gathered together for more effient bus utilization.
    • When performing uncached accelerated writes, the write buffer significantly reduces the number of write transactions On the external interface and reduces the amount of stalling in the core caused by the issuance of multiple writes in a Short period of time.
    • 写缓冲显著减少了外部接口上的写事务数量，并减少了内核中由于在短时间内发出多次写操作而引起的停顿。
    • 写缓冲可以将多个写操作收集在一起，然后执行突发写入，以提高总线的效率。支持对小于双字的任何大小进行不缓存的加速收集。

cache_enable 时的策略:
可缓存、一致性、写回、写分配、读缺失请求共享（代码＃5）： 维持一致性数据。加载缺失请求以共享状态请求数据（如果数据未被其他 CPU 共享，将获取独占状态）。多个缓存可以包含共享状态的数据。存储操作将数据带入缓存并处于独占状态 - 没有其他缓存可以包含相同的缓存行。如果存储命中了缓存中的共享行，该行将被更新为独占状态，并且其他 L1 数据缓存中的共享副本将被失效。

pma0cfg 控制 pmp0addr/pmp0cfg 对应的地址范围
…
pma63cfg 控制 pmp63addr/pmp63cfg 对应的地址范围

注意:
复用 csr, 策略同 pmpcfg/pmpaddr 寄存器:
pma0cfg-pma7cfg 共同组成 pmacfg0 csr
…
pma56cfg-pma63cfg 共同组成 pmacfg14 csr

RV64 中只用到
pmacfg0 pmacfg2 pmacfg4 pmacfg6 pmacfg8 pmacfg10 pmacfg12 pmacfg14 8 组寄存器
RV64:
pmacfg0:

pmacfg14:

pmp entry 的序号越小, 优先级越高. 如果多个 pmp entry 覆盖了同一段地址范围, 则按序号最小的 pmp entry 进行地址匹配.

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-: inaccessible (NO_PERM), =: accessible (ALL_PERM)

pmp[0]       |-------|                                | : memory 0
pmp[1]       |              |---------|               | : memory 1
pmp[2]       |       |==========|                     | : memory 2
pmp[others]  |                                        | : undefined
pmp[N]       |========================================| : memory N
result       |-------========---------================|

l2 cache coherence enable

对应 GCR.Core[0-63].COH_EN Register, 将该寄存器置 1, 代表开启 l2 coherence.
GCR_BASE offset: 0x020f8 + 0x100 * CORENUM
CORENUM 可以从 mhartid 中取得

CORENUM:

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csrr t0, mhartid
ext t1, t0, 4, 8 // t1 corenu

文档中没有找到可以单独配置 l2 cache CCA 属性.

cache 初始化

L1 icache 初始化

可以使用 MGINVI 或 FENCE.I 指令来初始化 icache.
? 不用清 cacheline 的 tag.

L2 cache 初始化

自动模式和手动模式

L2 cache 由硬件进行自动初始化

当下面条件满足时, 由硬件自动对L2 cache 初始化:
外部 pin si_cpc_l2_hw_init_inhibit 拉低, 表明可以由硬件自动初始化

• 设置 CPC_CL_STAT_CONF_REG (CPC 0x0008 offset) 的 L2_HW_INIT_EN bit
• 超出 L2 初始化开始倒计时的时延 delay 后, 硬件自动开始初始化流程
• MBIST 未启用, 如果启用了 MBIST, 只有当 MBIST 完成后才开始初始化流程
• 初始化完成后, GCR_L2_RAM_CONFIG (GCR offset 0x0240) 的 HCI_DONE 位会被硬件置1,  软件可以查询该 bit 确定 L2 cache 是否已经被初始化完成.

MBIST 内存自检测（Built-In Self-Test，BIST)
MIPS 支持 BIST 以测试 l2-cache.

L2 cache 手动被硬件初始化

可以选择只初始化 tag ram, 或初始化l2 cache line的 tag 和 data ram, 当下面条件满足时:
外部pin si_cpc_l2_hw_init_inhibit 拉高, 表明不进行自动硬件初始化

由软件进行初始化:

1. 读取 GCR_L2SM_COP (GCR 0x0620 offset) 的 L2SM_COP_REG_PRESENT [31]位, 值为1表示支持 flush l2 cache 操作
2. 读取 GCR_L2SM_COP 的 L2SM_COP_MODE [5] 位, 这个位值必须为0, 表明此时可以进行 cache 初始化
3. 软件重置 L2 cache 的 TAG RAM 或重置 TAG 和 DATA RAM, 操作 GCR_L2_TAG_ADDR (GCR 0x0600 offset) 和 GCR_L2_DATA (GCR 0x0610)
4. 设置 GCR_L2SM_COP 的 L2SM_COP_STATE [4:2] bit, 设置 0x1 表明 TAG RAM 已经被软件初始化, 设置为 0x2 表明 TAG DATA RAM 都已经被软件初始化
5. 设置 GCR_L2SM_COP 的 L2SM_COP_CMD [1:0] bit, 为 0x1, 表明开始进行 L2 cache 的初始化流程
6. 读取 GCR_L2SM_COP 的 L2SM_COP_RESULT [8:6] bit, 值为0 表明 L2 cache 的初始化流程正在进行中, 为 1 表明初始化流程已经完成且未发生错误.

cache 操作

• MCACHE：此指令用于对指令缓存（LI 缓存）、数据缓存和 L2 缓存执行各种操作。这些操作在后面详细介绍.
• PREF：此指令导致数据在缓存之间移动，以提高程序性能。REF 不会引发与地址相关的异常，包括 TLB 异常。
• FENCE.I: 在写入内存中的程序映像时，应使用此指令，以使新存储的指令操作码通过 I-Cache 对指令获取逻辑可见。相当于 mips 指令集的 SYNCI：此指令在 cluster 中的所有指令缓存上操作。在多 cluster 系统中, 对所有 L1 指令缓存上操作。
• MGINVT：这是 P8700-F 中的新指令，可用于使系统中的所有 L1 指令缓存无效。在多 cluster 系统中，这意味着在所有集群中的所有 L1 指令缓存上操作。

全局化指令只覆盖 l1-icache l2-cache, 没有覆盖 l1-dcache:

• FENCE.I 和 MCACHE I Hit Invalidate 指令是”全局化”的，这意味着它们将从系统中的所有 L1 指令缓存中使目标缓存行无效。
• 在多 cluster 系统中，MCACHE L2 Hit Invalidate、L2 Hit Writeback 和 L2 Hit Writeback Invalidate 操作也被全局化，将在系统中的所有 L2缓存上执行指定的操作（包括为维护包容性所需的任何 LI D-Cache 操作）。

#TODO 确认是否可以作用在多 cluster 间 @yifan.lin

注意，P8700-F MPS 不会全局化 CACHE D Hit Invalidate、D Hit Writeback 或 D Hit Writeback Invalidate 指令；这些指令只会影响执行该指令的核心的 LI D-Cache。

PREF

指令

PREF hint, imm($rs1)

hint 代表 type

• hint[4:3]
  • 0 - l1_icache
  • 1 - l1_dcache
  • 2 - l2_cache
  • 3 - l3_cache
• Hit[2:0]
  • 0 - load
  • 1 - store (不为 l1 icache)
  • 7 - prepareForStore (不为 l1 icache 时)
    • 如对应 cache line 未命中, 逐出或 invalidate 该 cache-line, 并将 cache line 的 data 填 0, 更新 cache line 为 modify 状态; 如 cache line 命中, 则只更新 cache line 为 Modify 状态.
      imm 偏移量
      rs1 地址
      

预取操作不会影响被 lock 的 cache line.
多核方案中, 该指令会修改 cache-line 状态, 意味着可能会导致另一个处理器的 cache-line 状态变更, 可能导致其他 core 的数据被逐出

L2 Prefectch

L2 预取操作使用两个 CM 的寄存器进行配置.

• GCR_L2_PFT_CONTROL (GCR_BASE offset 0x0300)
• GCR_L2_PFT_CONTROL_B (GCR_BASE offset 0x0308)
  这些控制寄存器支持以下 feature:
• 地址段可选 4k, 8k, 16k, 32k, 64k
• prefetch enable
• code prefetch enable
• coherent invalidate requests
• l2 prefetch cm port id, 每个 bit 对应 cm 的一个端口 id, 设置 portid 后, 对应的 CM 端口被控制进行预取.

prefetch 使能

数据预取
通过配置 GCR_L2_PFT_CONTROL 的 PFTEN [8] bit 置 1 使能.
PAGE_MASK [31:12] 设置地址段.
NPFT [7:0] 只读, 软件可以查询该位确定预取的单元总数. #TODO

CM 端口

共 8 个 CM 端口可用来选择进行 l2 prefetch
可以操作 GCR_L2_PFT_CONTROL_B 的 PORT_ID [7:0] 位选择开启对应 port_id 的预取.
该字段的每个 bit 对应一个端口.
可以有多个 core 和 iocu 的组合.
该字段的组织方式由 core 开始, 如 4 core, 2 iocu.
则 0-3 bit 代表 core0-3, 4-5 代表 iocu 0-1

代码预取

除数据预取外, CM 还支持代码预取
可通过 GCR_L2_PFT_CONTROL_B 的 CEN [8] bit 启用代码预取.

mcache

mcache 操作

缓存操作用于控制操作，如初始化、失效、驱逐等。以下是缓存操作的简要描述：

1. 索引写回失效（Index Writeback Invalidate）：如果指定索引处的缓存行状态为有效且脏，该行将被写回到由缓存标记指定的内存地址。完成该操作后，缓存行的状态将设置为无效。如果行有效但不脏，则将行的状态设置为无效。
2. 索引加载标记（Index Load Tag）：读取指定索引处缓存行的标记地址、标记状态和标记 ECC 位。还会读取数据 RAM 中的双字数据和 ECC。
3. 命中失效（Hit Invalidate）：如果缓存包含指定地址，该缓存行的状态将设置为无效。
4. 命中写回失效（Hit Writeback Inv）：如果缓存包含指定地址且该行有效且脏，该行的内容将写回到主存。完成该操作后，缓存行的状态将设置为无效。如果行有效但不脏，则将行的状态设置为无效。
5. 命中写回（Hit Writeback）：如果缓存包含指定地址且该行有效且脏，该行的内容将写回到主存。完成操作后，行的状态保持有效，但脏状态被清除。
6. 索引存储标记（Index Store Tag）：写入指定索引处缓存行的地址、标记状态、LRU 位和双字数据。可以选择写入 ECC，或者让硬件根据加载的双字生成 ECC。
7. 获取并锁定（Fetch And Lock）：如果缓存包含指定地址，锁定该行。如果缓存不包含指定地址，从主存重新填充该行，然后锁定该行。

mcache 指令

rs1 为寄存器

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// 将addr  line_size 对应的低位置0 后,  放到某一个通用寄存器中, 将寄存器号传给mcache
asm volatile("mcache %0,(%1)"::"i"(op),"r"(addr));
mcache op,(csr_no)
ihb //instruction hazard barrier, 执行mache后需要运行ihb, 表示接下来的取指依赖mcache 执行的结构

• I - l1-icache
• D - l1-dcache
• S - l2-cache
  
  
  
  
  其中涉及到的 L2 的 GCR 寄存器见下一章详细介绍, 其用法已经在表格中列出
  但是涉及到的 iTagLo/DtagLo/iDataHi/idatalo/DDataLow/DDataLo/DDataHi 寄存器未在其他文档中找到, 需要确认这个地方是否实现了, 是否是抄的 mips 文档抄错了? #TODO

ECC

l1 cache 和 l2 cache 均支持 ecc (error checking and correction)
对于 single-bit 单 bit 翻转错误, 硬件支持纠错恢复, 对软件是透明的
当检测到 2 bit 错误, 会产生异常.
超过 2 bit, 不操作.

对 l1-icache, 仅支持 edc (error detection), 当检测到数据损坏时, 会重新从地址中取指令, 该操作对于软件是透明的.

GCR

GCR.Global.L2_DATA

GCR_BASE 0x0610

L2 load tag mcache 指令, 将读取到的 L2 cacheline data 数据保存到了 GCR.Global.L2_DATA 寄存器中.
L2 store tag/data mcache 指令, 将 GCR.Global.L2_DATA 数据 dword index 加载到 l2 对应地址的 cacheline data 中.

GCR.Global.L2_TAG_ADDR

GCR_BASE 0x0600

L2 Load tag 指令, 将 L2 tag rams 加载到该寄存器
L2 store tag 指令, 将该寄存器内容保存到 L2 tag ram.

TAG_ADDR 保存 L2 Tag Ram entry 的地址部分,

GCR.Global.L2_TAG_STATE

GCR_BASE 0x0608
mcache 对某地址进行 L2 LOAD TAG 操作后, 会将对应的 cacheline tag state 加载到该寄存器.
mcache 对某地址进行 L2 STORE TAG 操作前, 可以写该寄存器, 设置 L2 cacheline 的 tag state.

GCR.Glocal.L2_RAM_CONFIG

GCR_BASE 0x240
HCI_DONE [30] bit 表示 l2 cache 已经被硬件初始化完成
见 L2 cache 由硬件进行自动初始化

GCR.Global.L2SM_COP

GCR_BASE 0x0620
见 L2 cache 手动被硬件初始化

GCR.GLOBAL.L2_PFT_CONTROL

GCR_BASE 0x0300
见 L2 Prefectch

GCR.GLOBAL.L2_PFT_CONTROL_B

GCR_BASE 0x0308
见 L2 Prefectch

case 验证

通过的 case:

• cache 使能
• self modify 的 icache 指令刷新功能的验证
• mcache 的 Hit_Wb_Inv_D Hit_Wb_Inv_S Hit_Inv_D Hit_Inv_S 操作初步验证

未进行的 case:

• 涉及 cache line 的 tag/data 的测试, 未进行, 资料不全, 缺少 iTagLo/DtagLo/iDataHi/idatalo/DDataLow/DDataLo/DDataHi 寄存器的介绍.
• cache flush invalidate wb 等的压测
• l2 禁用测试 #TODO l2 coherence 不开有什么影响, 贴结果?
• 多核一致性测试

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{"type":"excalidraw","version":2,"source":"https://excalidraw.com","elements":[],"appState":{"theme":"dark","gridSize":null,"viewBackgroundColor":"#ffffff"}}

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csr

target/riscv/csr.c

新增

• mipstvec
• mipsintctl
• mipsconfig6 空实现
• mipsconfig7 空实现
• marchid
• pmacfg0-pmacfg15

helper 指令集相关

target/riscv/cpu_helper.c

riscv_cpu_update_mip_from_pin

在 hip 中，我们将 CIP201P 到 CIP191P 和 LCOFIP 进行镜像处理，因为它们可以通过 hideleg 委派到虚拟模式，而所有可以委派的位在 hip 中都进行了镜像。我们也在 sip 中镜像了这些位，因为非 H 扩展的监管软件会查看该 CSR 来查看哪些中断是待处理的。至于是否需要在 hip 中镜像这些位，目前标记为待办事项[ #TODO ]，具体是否需要取决于实际需求和设计考虑。

H-extension 相关

与 riscv 公版对比

无 HVIP csr

wave qemu 中并没有对 H 相关的 csr 和指令进行修改, 采用的是 5.0 公版的
其行为与当前的 qemu 8.0 上最新规范不一样是正常的.
另外无法确定 H-extension 在 qemu 上的行为是否与开发板一致.

组件

cmgcr
cps
cpc

mtime 来自于 cpc 读取 rtc 时钟.

指令

lwp
swp
ldp
sdp
lsa
lsa_w
mcache
extins
zba zbb ccmov

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Text Elements

Source ^jENEYj0t

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Attestation
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pub key ^IPuKghKB

Attestation
CA ^jf35oBjr

signature ^YhW98mwR

Root
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signature ^TFM6hvTi

pub key ^c8ScYfTq

pub key ^8ll4rIEo

校验链 ^BGTRqeqL

priv key ^j4FfjOmM

priv key ^1hiboPOO

priv key ^x2dkXUTC

校验 ^jh9JHuXJ

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生成 ^ZTy1Nf0f

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